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Cadence PVS (Physical Verification System)

最佳芯片驗證工具

Cadence® Physical Verification System(PVS) 是由 EDA 軟件商 Cadence 所提出之新一代芯片驗證工具,它不僅能使用(yòng)于類比 / 數字 / 混合信号之設計平台,如 Virtuoso IC Layout Platform、Encounter,且更與寄生參數萃取軟件集成,如 QRC,以萃取布局後寄生參數,提供用(yòng)戶在芯片後段驗證的(de)完整解決方案。

随著(zhe)半導體制程的(de)發展趨勢,芯片後段驗證 (Back-end Verification) 所耗費的(de)處理(lǐ)時(shí)間與複雜(zá)度不斷提升的(de)情況下(xià),Cadence® Physical Verification System (PVS) 驗證工具,憑其線性化(huà)的(de)優異性能表現(Performance),不僅能減少運算(suàn)處理(lǐ)時(shí)的(de)等待時(shí)間;另外其創新的(de)實時(shí)偵錯 (Time-To-Error) 功能,實時(shí)偵錯已運算(suàn)完成部份,讓使用(yòng)者不再浪費時(shí)間等待運算(suàn)結果,再者,其新創的(de)人(rén)性化(huà)圖形除錯界面 (Graphic LVS Debug Interface ) 及交互式短路偵察系統 (Interactive Short Locator),不僅能有效彌補偵錯經驗不足的(de)困擾,更能有效縮短來(lái)回除錯所耗費的(de)時(shí)間 (Turn Around Time),以提升工程師的(de)效率及芯片産出。

此外,Cadence® Physical Verification System(PVS) 不僅同時(shí)支持 GDSII 與 Open-Access 的(de)格式,亦兼容于目前工業界标準的(de)驗證語言,以降低工程師跨平台使用(yòng)上的(de)額外工作與難度。

Physical Verification System (PVS) 流程圖

Physical Verification System (PVS) 後段驗證解決方案

Physical Verification System (PVS) 特點

成功經驗

超過 50 位以上使用(yòng)客戶,包括晶圓廠及芯片設計公司

使用(yòng)不同晶圓廠之不同制程下(xià)投片成功,包括成熟制程,如 130 / 90 / 65nm 及先進制程,如 45 / 40 / 28nm

競争力的(de)性能表現

優異的(de)單處理(lǐ)器 (singleCPU) 運算(suàn)性能

支持單機多(duō)核心或多(duō)機多(duō)核心

線性化(huà)運算(suàn)處理(lǐ)能力

有效率的(de)分(fēn)析及偵錯接口

集成式偵錯環境

實時(shí)偵錯 (Time to Error)

圖形化(huà)除錯接口 (Graphic LVS Debug Interface)

交互式短路偵查系統 (Interactive ShortLoctor)

跨平台集成

集成 Virtuoso customer IC layout platform 與 Cadence digital IC Encounter platform

集成 Cadence QRC extraction,提升布局後寄生參數萃取之完整流程

晶圓廠級的(de)設計服務

配合晶圓廠 Process Design Kits (PDK) 提供芯片設計所需文件數據

相容于台積電驗證之 iDRC / iLVS design kits

轉換無障礙

相似之用(yòng)戶接口,熟悉度高(gāo)易上手,操作無障礙

内建類似業界标準與法之 DRC / LVS 命令文檔,兼容性高(gāo)

支持業界标準語法之 DRC / LVS 命令文文件

PVS DRC

Easy to use one window interface

Time to error

- Error Browser will pop up and allow viewing of errors while job is still running

Standard DRC Browsing capabilities

- By Cell/ By Rule

Error Waivers

- Persistent and loadable in subsequent runs

Time To Error

Error Browser will pop up and allow viewing of errors while job is still running.

PVS LVS

Rapidly identifies complex LVS mismatches

Graphic LVS Debug accelerates identification of complex LVS mismatches in chip designs

- Compares logical and physical design using a common schematic representation

- Guides navigation using design errors

- Can be launched with LVS debug environment, and graphical elements can be probed through the LVS debug environment

- All errors and warnings are easily navigated and show surrounding context

Strong functionalities and flexible usability

Error Tags

World view or detail view

Filter net, devices for better understanding of error

Drill down for more information on points of interest

etc

LVS Hyper window - Graphical LVS Debug

LVS debug is extremely time-consuming and experience dependent

Limitation of current tools

- Static error report in batch mode, contain large data, difficult to understand

- Errors in text report hard to identify relationship

- User cannot actively query more information on points of interest

- Not allow easy navigation of the original design

Bind-key - Cadence Composor like

One-pass short isolation

Locating shorts found in old-fashion LVS comparison report requires

- Additional manual work

- Additional LVS extraction and comparison runs

PVS approach facilitates one-pass short isolation for cell / block / full-chip designs

- Run time typically <10% of extraction time and scales up to 5x with 8 CPUs

- Start debugging while run is in progress as soon as first results are available

Interactive Short Locator - Comparison with and without the Interactive Short Locator

PVS to QRC interface

Fully solution for back-end verification

Support Cadence QRC flow to complete post-layout simulation

No additional licenses required to enable flow

Provides complete QRC GUI support

TECHLIB feature makes PVS QRC flow easy to use

Batch / interactive use model

Support Spice, SPEF, DSPF, extracted view, etc. flows

Parity of flow between PVS / Assura = easy transition